The present invention relates to a lead frame for use in a land grid array (LGA) type resin-encapsulated semiconductor device.
In recent years, a resin-encapsulated semiconductor device of a type called xe2x80x9cQFNxe2x80x9d (quad flat non-leaded package) has been developed in the art, in which an encapsulation resin is provided substantially only on the upper side of a lead frame (i.e., the lead frame is molded on one side), in an attempt to realize a small and thin resin-encapsulated semiconductor device. A conventional QFN type resin-encapsulated semiconductor device in which a die pad is exposed on the reverse surface of the package will now be described.
FIG. 11 is a cross-sectional view illustrating a conventional QFN type resin-encapsulated semiconductor device. FIG. 12 is a plan view illustrating a lead frame used in the conventional QFN type resin-encapsulated semiconductor device. As illustrated in FIG. 12, the lead frame used in the conventional resin-encapsulated semiconductor device includes an outer frame 107, or a frame body, having an opening therein, a rectangular die pad 101 placed substantially in the center of the opening, suspension leads 108 each having one end connected to a corner of the die pad 101 and the other end connected to the outer frame 107 for supporting the die pad 101, and a plurality of inner leads 103 each extending toward the corresponding side of the die pad 101. The conventional QFN type resin-encapsulated semiconductor device (package) includes the die pad 101, the suspension leads 108 and the inner leads 103 of the lead frame, a semiconductor chip 102 bonded on the die pad 101 of the lead frame, thin metal wires 104 electrically connecting electrodes of the semiconductor chip 102 with some of the inner leads 103, and an encapsulation resin 105 encapsulating the semiconductor chip 102, the inner leads 103, the thin metal wires 104, the suspension leads 108 and the die pad 101 together on the upper side of the lead frame. Note however that the reverse surface of the die pad 101, and the reverse surface and the outer side surface of each inner lead 103 are not covered with the encapsulation resin 105 but are exposed on the reverse surface or the side surface of the package. The reverse surface portion and the outer side surface portion of each inner lead 103 function as an external terminal 106.
Note that although FIG. 12 only shows, as a unit, a region of the lead frame on which one semiconductor chip is mounted, the entire lead frame actually includes a plurality of such units as illustrated in FIG. 12 that are arranged next to each other in a matrix pattern.
Next, a method for manufacturing the conventional QFN type resin-encapsulated semiconductor device will be described. FIGS. 13A to 13D are cross-sectional views taken along line XIIIxe2x80x94XIII of FIG. 12, illustrating the method for manufacturing the conventional resin-encapsulated semiconductor device.
First, in the step of FIG. 13A, a lead frame as illustrated in FIG. 12 is prepared, including the die pad 101 on which the semiconductor chip is mounted, suspension leads (not shown) for supporting the die pad 101, and the inner leads 103 each extending toward the corresponding side of the die pad 101 (see FIG. 11).
Next, in the step of FIG. 13B, the reverse surface of the semiconductor chip 102 is bonded on the upper surface of the die pad 101 via an adhesive, and the semiconductor chip 102 is mounted on the die pad 101 of the lead frame.
Next, in the step of FIG. 13C, the semiconductor chip 102 and a bonding region of the upper surface of each inner lead 103 are electrically connected to each other via the thin metal wire 104.
Then, in the step of FIG. 13D, the lead frame having a number of semiconductor chips mounted thereon is set in an encapsulation mold set, with a sheet material (not shown) being closely held on an upper mold or a lower mold of the encapsulation mold set, and a resin encapsulation process is performed, whereby the semiconductor chip 102, the inner leads 103, the thin metal wires 104, the suspension leads 108 and the die pad 101 are encapsulated in the encapsulation resin 105 on the upper side of the lead frame. At this time, the reverse surfaces of the die pad 101 and each inner lead 103 are exposed, i.e., not covered with the encapsulation resin 105. Then, the lead frame is cut along the side surface of the encapsulation resin 105 so as to be divided into individual packages. In each package (resin-encapsulated semiconductor device), the reverse surface portion and the outer side surface portion of each inner lead 103 function as an external terminal 106.
Although the above-described conventional QFN type resin-encapsulated semiconductor device has an innovative structure as a small and thin semiconductor device, there is much to be improved in order to accommodate a further increase in the number of pins of a semiconductor chip to be mounted and a further reduction in size. In view of this, an LGA type resin-encapsulated semiconductor device has been recently proposed in the art, in which external terminals are provided in two rows on the reverse surface of a package, in order to further reduce the size of the device and to increase the number of external terminals.
FIGS. 14A to 14C are an top view, a bottom view and a cross-sectional view taken along line XIVcxe2x80x94XIVc, respectively, each illustrating an LGA type resin-encapsulated semiconductor device proposed in the prior art. FIG. 15 is a plan view illustrating a lead frame used in the LGA type resin-encapsulated semiconductor device. As illustrated in FIG. 15, the lead frame used in the conventional resin-encapsulated semiconductor device includes an outer frame 107, or a frame body, having an opening therein, a rectangular die pad 101 placed substantially in the center of the opening, suspension leads 108 each having one end connected to a corner of the die pad 101 and the other end connected to the outer frame 107 for supporting the die pad 101, a plurality of first inner leads 103a each extending toward the corresponding side of the die pad 101, and a plurality of second inner leads 103b each extending to a position closer to the die pad 101 than the first inner leads 103a. 
As illustrated in FIGS. 14A to 14C, the LGA type resin-encapsulated semiconductor device (package) includes a semiconductor chip 102 bonded on the die pad 101, the first and second inner leads 103a and 103b, thin metal wires 104 electrically connecting the semiconductor chip 102 with the first and second inner leads 103a and 103b, and an encapsulation resin 105 encapsulating the semiconductor chip 102, the inner leads 103a and 103b, the thin metal wires 104, the suspension leads (not shown) and the die pad 101 together on the upper side of the lead frame. Note however that the reverse surface of the die pad 101, the outer side surface and the reverse surface of each first inner lead 103a, the outer side surface of each second inner lead 103b, and the reverse surface of the tip portion of each second inner lead 103b are not covered with the encapsulation resin 105 but are exposed on the side surface or the reverse surface of the package. The reverse surface and the outer side surface of each first inner lead 103a, which are exposed respectively on the reverse surface and the side surface of the package, function as a first external terminal 106a. The reverse surface of each second inner lead 103b, which is exposed on the reverse surface of the package at a position closer to the die pad 101 than the first external terminal 106a, functions as a second external terminal 106b. Note that a lower portion of each second inner lead 103b is removed through a half-etching process except for the tip portion thereof, so that the second inner lead 103b has a reduced thickness in the half-etched portion.
Note that although FIG. 15 only shows, as a unit, a region of the lead frame on which one semiconductor chip is mounted, the entire lead frame actually includes a plurality of such units as illustrated in FIG. 15 that are arranged next to each other in a matrix pattern.
Next, a method for manufacturing the conventional LGA type resin-encapsulated semiconductor device will be described. FIGS. 16A to 16D are cross-sectional views taken along line XVIxe2x80x94XVI of FIG. 15, illustrating the method for manufacturing the resin-encapsulated semiconductor device.
First, in the step of FIG. 16A, a lead frame is prepared, including the die pad 101 on which the semiconductor chip is mounted, the first inner leads 103a each extending toward the corresponding side of the die pad 101, and the second inner leads 103b each extending to a position closer to the die pad 101 than the first inner leads 103a (see FIG. 15).
Next, in the step of FIG. 16B, the semiconductor chip 102 is bonded and mounted on the die pad 101 of the lead frame via an adhesive.
Next, in the step of FIG. 16C, the semiconductor chip 102 and a bonding region of the upper surface of each of the first and second inner leads 103a and 103b are electrically connected to each other via the thin metal wire 104.
Then, in the step of FIG. 16D, the lead frame having a number of semiconductor chips mounted thereon is set in an encapsulation mold set, with a sheet material (not shown) being closely held on an upper mold or a lower mold of the encapsulation mold set, and a resin encapsulation process is performed, whereby the semiconductor chip 102, the inner leads 103a and 103b, the thin metal wires 104, the suspension leads 108 and the die pad 101 are encapsulated in the encapsulation resin 105 on the upper side of the lead frame. At this time, the reverse surface of the die pad 101, the reverse surface and the outer side surface of each first inner lead 103a, the reverse surface of the tip portion of each second inner lead 103b, and the outer side surface of each second inner lead 103b are exposed, i.e., not covered with the encapsulation resin 105. Then, the lead frame is cut along the side surface of the encapsulation resin 105 so as to be divided into individual packages. In each package (resin-encapsulated semiconductor device), the reverse surface portion and the outer side surface portion of each first inner lead 103a function as the first external terminal 106a. The reverse surface portion of the tip portion of each second inner lead 103b, which is at a position closer to the die pad 101 than the first external terminal 106a, functions as the second external terminal 106b. 
Although the above-described conventional QFN type resin-encapsulated semiconductor device has a reduced size and a reduced thickness, it has not been sufficient for accommodating a further increase in the number of pins. While the above-described conventional LGA type resin-encapsulated semiconductor device accommodates an increased number of pins and has two rows of external terminals, there is a demand for such devices with more than two rows of external terminals. LGA type resin-encapsulated semiconductor devices having three or more rows of external terminals have encountered other problems caused by the increased number of rows of external terminals.
In order to increase the efficiency of the manufacturing process, an LGA type resin-encapsulated semiconductor device having three or more rows of external terminals is manufactured by the following process, for example. That is, a plurality of units each including a chip mounted thereon are provided in a single lead frame, and the entire surface of the lead frame is resin-encapsulated at once by using an encapsulation resin such as an epoxy resin, after which the encapsulated lead frame is cut by a rotating blade such as a dicer into individual packages (resin-encapsulated semiconductor devices) each including a chip. In the step of dividing the lead frame, which has been resin-encapsulated at once, into pieces by using the rotating blade, stripping may occur at the interface between the leads and the encapsulation resin, thus lowering the reliability of the product. Even after the encapsulated lead frame is divided into individual packages (resin-encapsulated semiconductor devices) by using the rotating blade, stripping may occur at the interface between the leads and the encapsulation resin when a stress is applied to a resin-encapsulated semiconductor device, thus lowering the reliability of the product.
An object of the present invention is to provide a lead frame used for producing a resin-encapsulated semiconductor device having three or more rows of lands (external terminals) on the reverse side of the resin-encapsulated semiconductor device.
A lead frame of the present invention includes: a frame body made of a conductive material and including at least one opening for mounting a semiconductor chip; a die pad placed in the opening of the frame body; and a group of leads extending from the frame body into the opening. The group of leads include at least: a first lead connected to the frame body and including a first bonding pad provided on an upper surface of the first lead and a first land provided on a lower surface of the first lead; a second lead connected to the frame body and including a second bonding pad provided on an upper surface of the second lead and a second land provided on a lower surface of the second lead; and a third lead connected to the first lead and including a third bonding pad provided on an upper surface of the third lead and a third land provided on a lower surface of the third lead. A connecting portion that is thinner than the lead frame body and that can be punched through is provided between the first lead and the third lead.
In this way, upon production of the lead frame, the third lead is connected to the frame body and is supported by the frame body. Then, the connecting portion is punched through in a subsequent step, whereby the first lead and the third lead can be used while being electrically separated from each other. Therefore, a large number of lands, i.e., the first, second and third lands, can be used as external terminals without increasing the number of leads that are connected to the periphery of the opening. Thus, it is possible to obtain a lead frame useful for producing a semiconductor device having three or more rows of external terminals.
At least the second lead may include a neck portion having a smaller width than other portions as viewed in a plan view. In this way, when the first, second and third leads are incorporated in a resin-encapsulated semiconductor device, the leads and the encapsulation resin contact each other over an increased contact area at the neck portion, whereby even if stripping occurs between the leads and the encapsulation resin, the progress of the stripping can be suppressed.
Each lead may include a region around the bonding pad thereof that has a smaller thickness than that of a portion of the lead corresponding to the bonding pad, with a stepped portion being provided between the bonding pad and the region around the bonding pad. Also in this way, the progress of the stripping between the leads and the encapsulation resin can be suppressed.
The first, second and third lands may be substantially coplanar on a common plane while being arranged in three rows on the common plane.
It is preferred that the second lead and a lead structure including the first and third leads are arranged alternately along a periphery of the opening of the frame body.
It is preferred that the frame body, the die pad and the group of leads are made of a single metal plate.